One-time programming multiple-level memory cells
US7002832B2 · kind B2 · utility
9Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Oct 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-level memory cell including a storage element formed of several polysilicon resistors connected in series between two input/output terminals; and a load in series with said resistive element, the midpoint of this series connection forming a read terminal of the memory cell, and the respective junction points of said resistors of the storage element being accessible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.