SRAM-compatible memory device having three sense amplifiers between two memory blocks
US7002864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jul 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The SRAM-compatible memory device includes a first pair of bit lines for transferring data fetched from/written in a DRAM cell in a first memory block, a second pair of bit lines for transferring data fetched from/written in a DRAM cell in a second memory block. Further, the SRAM compatible memory device includes the first sense amplifier for amplifying and latching data in the first pair of bit lines, a second sense amplifier for amplifying and latching data in the second pair of bit lines, a third sense amplifier for amplifying and latching data transferred whereto, a first switching unit for controlling an electrical connection between the first pair of bit lines and the third sense amplifier, and a second switching unit for controlling an electrical connection between the second pair of bit lines and the third sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.