PLL cycle slip detection
US7003065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jun 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2π radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.