Digital phase locked loop with phase selector having minimized number of phase interpolators
US7003066B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.