Method and a device for monitoring the performance of test apparatus for testing components
US7003416B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Apr 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for monitoring the performance of a test apparatus (1) for testing a batch of integrated circuits. The apparatus 1 comprises a test site 2 in which the integrated circuits are sequentially tested, and a microprocessor (4) for carrying out the appropriate tests on the integrated circuits. A first ROM (5) stores a computer programme for controlling the operation of the microprocessor (4) for carrying out the tests, and a first RAM (10) stores a computer programme for controlling the operation of the microprocessor (4) for monitoring the performance of the test apparatus (1). In particular, the computer programme stored in the first RAM (10) operates the microprocessor (4) for computing the test time period for each integrated circuit tested, and also for computing the intervening time periods between each integrated circuit tested. The intervening time periods between the respective test time periods are classified as either first or second category delays or index time periods. An index time is the normal time required between tests. A first category time delay is one which exceeds thirty seconds, while a second category time delay is one which lies between four seconds and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.