Process and apparatus for finite field multiplication (FFM)
US7003538B2 · kind B2 · utility
1Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Feb 8, 2002 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2n described by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n−2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.