High performance carry chain with reduced macrocell logic and fast carry lookahead
US7003545B1 · kind B1 · utility
7Cited by
12References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 11, 2001 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.