Method, apparatus and computer program product for dynamically minimizing translation lookaside buffer entries across contiguous memory
US7003647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Apr 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.