Detection circuit and method for clearing BIOS configuration memory
US7003655B2 · kind B2 · utility
9Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A BIOS configuration memory-clearing detection circuit and a method of clearing a BIOS configuration memory for computer main board uses a latching circuit to detect whether a user has set a clearing of the BIOS configuration memory. If the user has set a clearing of the BIOS configuration memory, the latching circuit sets a clearing latch signal. When the computer subsequently switches on, a ROM BIOS reads the status of the clearing latch signal. If the clearing latch signal is set, the ROM BIOS further clears the BIOS configuration memory to ensure the clearing operation is successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.