Performance modeling for circuit design
US7003745B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.