Zero threshold voltage pFET and method of making same

US7005334B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey S. Brown · Jeffersonville, US
• Chung H. Lam · Williston, US
• Randy W. Mann · Jericho, US
• Jeffery H. Oppold · South Burlington, US

Key dates

• Filing date: May 14, 2004
• Grant date: Feb 28, 2006
• Expiry date: May 14, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).