Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling

US7005708B2 · kind B2 · utility

Assignees

• Sarnoff Corporation · US
• Sarnoff Europe · BE

Inventors

• Markus Mergens · Plainsboro, US
• Koen Gerard Maria Verhaege · Gistel, BE
• Cornelius Christian Russ · Diedorf, DE
• John Armer · Middlesex, US
• Phillip Czeslaw Jozwiak · Plainsboro, US
• Bart Keppens · Gistel, BE

Key dates

• Filing date: May 12, 2003
• Grant date: Feb 28, 2006
• Expiry date: Jul 9, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/48091

Abstract

An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.