Methods and apparatus for injecting an external clock into a circuit
US7005885B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.