Patent · US Expired

High-performance clock-powered logic

US7005893B1 · kind B1 · utility

11Cited by

13References

29Claims

0Family size

Assignee

University of Southern California · US

Inventors

William C. Athas · San Jose, US
Nestor Tzartzanis · Belmont, US
Weihua Mao · San Jose, US
Lena Peterson · Gothenburg, SE

Key dates

Filing date	Jul 18, 2000
Grant date	Feb 28, 2006
Priority date	—
Expiry date	Jul 18, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0019
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.