Low noise YIG oscillator based phase locked loop
US7005927B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | May 28, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low phase noise YIG oscillator based phase locked loop couples an output frequency to a delay line discriminator to provide a phase noise feedback signal to a wideband tuning port of the YIG oscillator. A delay line in the delay line oscillator may be implemented with either a resonant circuit or a bandpass filter of sufficient bandwidth so that the output frequency and phase noise sidebands are not attenuated. The resonant circuit may be implemented as a YIG sphere integrated into the YIG oscillator in the same magnetic path as the YIG sphere in the oscillator circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.