Semiconductor storage device and refresh control method thereof
US7006401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2002 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.