External bus arbitration technique for multicore DSP device
US7006521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.