Cipher block chaining mode in encryption/decryption processing
US7006627B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Feb 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.