Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output
US7007053B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2218/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The coefficient block also enables an area minimal realization of digital filters based on the coefficient block, when operated in serial bit fashion. The optimization techniques and structure are good for bit-serial digital filters typically a finite impulse response (FIR) filter, including finite impulse response filter (IIR) and for other filters and applications based on combinational logic that includes delay elements, multipliers, and serial adders and/or subtractors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.