Accessing a primary bus messaging unit from a secondary bus through a PCI bridge
US7007126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jul 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (I2O®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.