Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US7007131B2 · kind B2 · utility
4Cited by
21References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method wherein a special programming mode of a memory is entered and internal program verification by the memory is disabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. The special programming mode is exited and internal program verification by the memory is enabled. The special programming mode may use hashing to optimize testing for a memory such as a nonvolatile flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.