Digital signal processor for wireless baseband processing
US7007155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.