Method and system for handling multiple bit errors to enhance system reliability
US7007210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2002 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jan 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N−x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.