Method and mechanism for RTL power optimization
US7007247B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Mar 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.