Method to provide a triple well in an epitaxially based CMOS or BiCMOS process
US7008836B2 · kind B2 · utility
121Cited by
11References
16Claims
0Family size
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Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Mar 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.