Mask ROM fabrication method
US7008848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Feb 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/383
Abstract
A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers. The word lines are formed to be parallel to each other, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to the buried impurity diffusion regions. The pad conductive layers, which form ohmic contacts with t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.