Thin film transistor with self-aligned intra-gate electrode
US7009204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jun 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
Abstract
A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.