Memory device and method of production and method of use of same and semiconductor device and method of production of same
US7009208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Apr 10, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
Abstract
A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines and the bit lines extend.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.