Digitally controlled delay cells
US7009433B2 · kind B2 · utility
24Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.