Output buffer with controlled slew rate for driving a range of capacitive loads
US7009435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Mar 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Output buffer slew rate variation over variations in load capacitance is minimized by dividing output voltage transitions into distinct time and output current segments. During the first time segment, the first drive stage with the smallest current is employed. After subsequent delays, additional drive stages are employed and the load current is sequentially increased. Each drive stage employs a specifically sized feedback device which, depending upon its dimensions will provide either parasitic capacitance to slow transitions or positive feedback to speed up transitions. The first stages are sized to incorporate parasitic capacitance, resulting in little change in the settling time of small capacitance loads over prior art output buffers. Latter stages use positive feedback to quicken the transition time which dramatically improves the settling time for larger load capacitances over prior art output buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.