Semiconductor memory device
US7009881B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Aug 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell unit with a plurality of electrically rewritable memory cells connected in series, two ends thereof being coupled to a data transfer line and a reference potential line via select transistors, respectively, wherein the device has a data read mode defined as to detect a read current flowing between the data transfer line and the reference potential line, and judge data of a selected memory cell in the memory cell unit under the condition of: applying a read voltage to the selected memory cell, the read voltage being set to turn on or off the selected memory cell in accordance with data thereof; applying a pass voltage to remaining unselected memory cells, the pass voltage being set to turn on the remaining unselected memory cells without regard to data thereof; and making the select transistors on, and wherein in the data read mode, the more unselected memory cell or cells located on the source side of the selected memory cell, the higher the pass voltage applied to the unselected memory cell or cells located on the source side of the selected memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.