Non-volatile semiconductor memory array and method of reading the same memory array
US7009890B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 12, 2002 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories. Moreover, the read timing of the reference memories is outputted as an external interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.