Dynamically activated memory controller data termination
US7009894B2 · kind B2 · utility
2Cited by
48References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Feb 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.