High performance wireless receiver with cluster multipath interference suppression circuit
US7010070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03592
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver which suppresses inter-cluster multipath interference by processing an impulse channel response consisting of two multipath clusters, each cluster having groups of signals with multiple delays. In one embodiment, the receiver includes a single antenna and parallel-connected delay units used to align the groups of signals before being input into respective sliding window equalizers. The outputs of the equalizers are combined at chip level via a combiner which provides a single output. In another embodiment, a Cluster Multipath Interference Suppression (CMIS) circuit is incorporated into the receiver. The CMIS circuit includes a hard decision unit and a plurality of signal regeneration units to generate replicas of the multipath clusters. The replicas are subtracted from the respective outputs of the delay units and the results are input to the respective sliding window equalizers. In another embodiment, multiple antennas are used to receive and process the clusters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.