Oversampling clock recovery having a high follow-up character using a few clock signals
US7010074B2 · kind B2 · utility
35Cited by
6References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Feb 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two edges of two-phase clock signals CLKb and CLKc having a relatively narrower interval of 57 ps synchronizes with a phase of a transition point of the input data i. By changing clock signals to be phase-locked in three delay locked loops (DLLs), a phase interval of 57 ps is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.