CMOS process silicon waveguides
US7010208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/132
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A standard CMOS process is used to fabricate optical and electronic devices at the same time on a monolithic integrated circuit. In the process, a layer of metallic salicide can be depsoited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into the core of an optical waveguide will damage the waveguide and prevent the passage of light through that section of the waveguide. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.