Data processor with enhanced instruction execution and method
US7010558B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2002 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Feb 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a user-configurable processor having an extension instruction adapted for reduced cycle-count algorithmic operations. In one exemplary embodiment, the processor is an extensible core, and the extension instruction comprises a 32-bit instruction word linked with existing circuitry in the processor core used for multiply-accumulate (mac) instructions. 16-bit, 24-bit, and dual 16-bit multiply options are available for the multiply/accumulate unit of the processor. The extension instruction is pipelined to the same number of stages as the mac instructions, thereby avoiding unnecessary stalls and increasing performance. A modified accumulator data path used in support of the foregoing instruction is also described. A computer program and apparatus for synthesizing logic implementing the aforementioned functionality are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.