Method and apparatus for memory management
US7010656B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an electronic device includes a processor, a physical memory coupled to the processor, and a storage medium coupled to the processor. The storage medium may store instructions which when executed by the processor cause the processor to: survey at least a portion of the physical memory, determine an amount of free memory space and used memory space based on the survey of the physical memory, determine if a consolidation of used memory space should be performed, and, if so determined, consolidate the used memory space, and reduce the power provided to at least a portion of the physical memory following the consolidation of used memory space. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.