Methods and apparatus for memory map generation on a programmable chip
US7010666B1 · kind B1 · utility
3Cited by
2References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for the automatic assignment of addresses for slave components to be implemented on a programmable chip. Slave components including peripheral components and peripheral interfaces are assigned to master components. In some examples, master components and slave components are analyzed using criteria such as address space availability and address span width to more efficiently assign base addresses for the various slave components on a programmable chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.