Prescaler architecture capable of non integer division
US7010714B1 · kind B1 · utility
6Cited by
7References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2001 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prescaler generally comprising a first circuit, a multiplexer, and a second circuit. The first circuit may be configured to present a plurality of control signals in response to a first clock signal having a first frequency. The multiplexer may be configured to multiplex a plurality of data signals in response to the control signals to present a second clock signal having a second frequency that is a non-integer fraction of the first frequency. The second circuit may be configured to present the data signals in response to the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.