Method for identifying removable inverters in an IC design
US7010765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | May 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node. Each data set points to all data sets corresponding to segments immediately downstream of the data set's corresponding segment, so that the data sets for all segments form a decision tree that may be traversed to determine which inverters must be removed to maximize the numbe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.