Semiconductor chip with passive element in a wiring region of the chip
US7012339B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2003 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Nov 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut from the wafer. In a case where a chip size package is made, the chip region is cut from the wafer after forming the redistribution wiring and external terminals and so forth over the whole of the chip region. As a result, the design of the integrated circuit and part of the fabrication process thereof can be shared by a chip which is mounted in a chip size package and a chip which is mounted in another type of package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.