Mixer circuit offset compensation
US7012457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2004 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0047
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixer circuit arrangement for frequency-translating a voltage input signal by an amount dependent on the frequency of a local oscillator signal to provide an output signal. The arrangement comprises an input stage 33 and a mixer stage 32, the input stage 33 being arranged to convert the voltage input signal into differential current signals and the mixer stage 32 being arranged to mix the differential current signals with the local oscillator signal to provide the output signal. Means 34,35 is provided for injecting a compensation current into the input stage 33 so as to balance the differential current signals provided to the mixer stage 32.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.