System and method generating a delayed clock output
US7012474B2 · kind B2 · utility
12Cited by
1References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Mar 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.