Transconductance device employing native MOS transistors
US7012487B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2001 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Apr 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/0422
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator element including a plurality of current sources interconnected to provide output transconductance voltages, and a variable load for the current sources including first and second load resistors each serially connected with one other plurality of current sources. A variable resistance interconnects nodes of the load resistors with the variable resistance comprising a pair of native MOS transistors having low threshold voltages. In a preferred embodiment the first and second load resistors comprise first and second MOS transistors with the pair of native transistors serially connected between source elements of the first and second MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.