PLL noise smoothing using dual-modulus interleaving
US7012984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.