High speed memory interface system and method
US7013359B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a high speed serial memory interface system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relatively slow speed serial communication rate. In one embodiment the present invention is a high speed serial memory interface system with an information configuration core for coordinating proper alignment of information communication signals, a system interface for communicating with a system controller, and a memory array interface for communicating with a memory array. A memory module array for storing information and a high speed serial memory interface system for providing interface configuration management are integrated on a single substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.