Method, program, and apparatus for designing a semiconductor device
US7013446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for designing a semiconductor device in which dummy pattern density and design pattern density are equalized on the entire semiconductor chip. A layout pattern for a layout layer in a semiconductor device is divided into divided areas (step S1). A dummy pattern is inserted between design patterns in the divided areas obtained by dividing the layout pattern (step S2). Dummy pattern density and design pattern density in each divided area are calculated (step S3). Pattern rules for a dummy pattern in each divided area are changed so that the dummy pattern density and the design pattern density will be desired values (step S4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.