Attestation key memory device and bus
US7013481B1 · kind B1 · utility
26Cited by
128References
80Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Mar 14, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.