Method of manufacturing a field effect transistor and a liquid crystal display using the same
US7015084B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting substantially the same function as the lightly doped drain regions, wherein the lightly activated high impurity concentration regions are bounded with high impurity concentration regions serving as source and drain regions. The boundaries are self-aligned to edges of a gate electrode. Side regions of the gate electrode overlap the lightly activated high impurity concentration regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.